Topic outline

  • Description

    This course covers performance engineering approaches on the compute node level. Even application developers who are fluent in OpenMP and MPI often lack a good grasp of how much performance could at best be achieved by their code. This is because parallelism takes us only half the way to good performance. Even worse, slow serial code tends to scale very well, hiding the fact that resources are wasted. This course conveys the required knowledge to develop a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. We introduce the basic architectural features and bottlenecks of modern processors and compute nodes. Pipelining, SIMD, superscalarity, caches, memory interfaces, ccNUMA, etc., are covered. A cornerstone of node-level performance analysis is the Roofline model, which is introduced in due detail and applied to various examples from computational science. We also show how simple software tools can be used to acquire knowledge about the system, run code in a reproducible way, and validate hypotheses about resource consumption. Finally, once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of code changes can often be predicted, replacing hope-for-the-best optimizations by a scientific process.

    This course provides –via lectures, demos, and hands-on labs– scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.

    This course is organized by the Vienna Scientific Cluster (VSC).



    • Our approach to performance engineering
    • Basic architecture of multicore systems: threads, cores, caches, sockets, memory
    • The important role of system topology

    Tools topology & affinity in multicore environments

    • Overview
    • likwid-topology and likwid-pin

    Microbenchmarking for architectural exploration

    • Properties of data paths in the memory hierarchy
    • Bottlenecks
    • OpenMP barrier overhead

    Roofline model: basics

    • Model assumptions and construction
    • Simple examples
    • Limitations of the Roofline model

    Tools: hardware performance counters

    • Why hardware performance counters?
    • likwid-perfctr
    • Validating performance models

    Roofline case studies

    • Dense matrix-vector multiplication
    • Sparse matrix-vector multiplication
    • Jacobi (stencil) smoother

    Optimal use of parallel resources

    • Single Instruction Multiple Data (SIMD)
    • Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
    • Simultaneous Multi-Threading (SMT)

    Extending Roofline: The ECM performance model

    Optional: Pattern-based performance engineering 


    Georg Hager and Gerhard Wellein (RRZE / HPC, Uni. Erlangen)



    Date, Time, and Location:

    March 10-12, 2021, 9am - 5pm,
    Online course via Zoom