Node-Level Performance Engineering @ TU Wien

Topic outline

• 

  Description

  This course covers performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy based on the Roofline model and apply it to different algorithms from computational science. Architectural details that are relevant for performance, such as pipelining, SIMD, superscalarity, memory hierarchies, etc., are covered in due detail.

  This course provides –via lectures, demos, and hands-on labs– scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.

  This course is organized by the Vienna Scientific Cluster (VSC).

  Content:

  Introduction

  • Our approach to performance engineering
  • Basic architecture of multicore systems: threads, cores, caches, sockets, memory
  • The important role of system topology

  
  Tools topology & affinity in multicore environments

  • Overview
  • likwid-topology and likwid-pin

  
  Microbenchmarking for architectural exploration

  • Properties of data paths in the memory hierarchy
  • Bottlenecks
  • OpenMP barrier overhead

  
  Roofline model: basics

  • Model assumptions and construction
  • Simple examples
  • Limitations of the Roofline model

  
  Tools: hardware performance counters

  • Why hardware performance counters?
  • likwid-perfctr
  • Validating performance models

  
  Roofline case studies

  • Dense matrix-vector multiplication
  • Sparse matrix-vector multiplication
  • Jacobi (stencil) smoother

  
  Optimal use of parallel resources

  • Single Instruction Multiple Data (SIMD)
  • Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
  • Simultaneous Multi-Threading (SMT)

  
  Extending Roofline: The ECM performance model

  Optional: Pattern-based performance engineering 
  

  
  

  Lecturers:

  Georg Hager and Gerhard Wellein (RRZE / HPC, Uni. Erlangen)

  Language:

  English

  Date, Time, and Location:

  March 24-26, 2020, 9am - 5pm,
  FH Internet-Raum FH1 (TU Wien, Wiedner Hauptstraße 8-10, ground floor, red area)

  
  
• 

  Day 1

  • Tentative agenda File
  • General intro (including answers to quiz) File
  • Introduction to core and node architecture File
  • Topology and affinity File
  • Microbenchmarking for architectural exploration (and more) File
  • Hands-on exercises. Note: For copying an example code to your current directory, type:
    
    

    $ cp -a ~ghager/<XXX> $PWD

    (Substitute <XXX> with the name of the folder you need)

    
    

    Live stream for the demos:

    
    

    http://typo3.vsc.ac.at/research/vsc-research-center/vsc-school-seminar/livestream/
    

  • Exercise: Measuring the divide instruction/operation throughput Page
• 

  Day 2

  • Introduction to the Roofline model File
  • Analysis with hardware performance counters File
  • Programming on ccNUMA nodes File
  • Single Instruction Multiple Data (SIMD) File
  • Simultaneous Multi-Threading (SMT) File
  • Exercise: The STREAM benchmarks Page
• 

  Day 3

  • Roofline case studies File
  • Exercise: General code optimization Page
  • Exercise: A simple stencil solver Page
• 

  Miscellaneous

  Links

  LIKWID tool suite: https://github.com/RRZE-HPC/likwid

  LIKWID documentation Wiki: http://tiny.cc/LIKWID

  LIKWID quick reference sheet: https://moodle.rrze.uni-erlangen.de/mod/resource/view.php?id=7024

  Kerncraft automatic Roofline/ECM modeling tool: https://github.com/RRZE-HPC/kerncraft

  Online layer condition calculator: https://rrze-hpc.github.io/layer-condition/

  
  

  Intel online intrinsics guide: https://software.intel.com/sites/landingpage/IntrinsicsGuide/

  
  

  GHOST sparse building blocks library: http://tiny.cc/GHOST

  PHIST, a Pipelined Hybrid Parallel Iterative Solver Toolkit: https://bitbucket.org/essex/phist