Description
This course covers performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy based on the Roofline model and apply it to different algorithms from computational science. Architectural details that are relevant for performance, such as pipelining, SIMD, superscalarity, memory hierarchies, etc., are covered in due detail.
This course provides –via lectures, demos, and hands-on labs– scientific training in Computational Science, and in addition, the scientific exchange of the participants among themselves.
This course is organized by the Vienna Scientific Cluster (VSC).
Content:
Introduction
- Our approach to performance engineering
- Basic architecture of multicore systems: threads, cores, caches, sockets, memory
- The important role of system topology
Tools topology & affinity in multicore environments
- Overview
- likwid-topology and likwid-pin
Microbenchmarking for architectural exploration
- Properties of data paths in the memory hierarchy
- Bottlenecks
- OpenMP barrier overhead
Roofline model: basics
- Model assumptions and construction
- Simple examples
- Limitations of the Roofline model
Tools: hardware performance counters
- Why hardware performance counters?
- likwid-perfctr
- Validating performance models
Roofline case studies
- Dense matrix-vector multiplication
- Sparse matrix-vector multiplication
- Jacobi (stencil) smoother
Optimal use of parallel resources
- Single Instruction Multiple Data (SIMD)
- Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
- Simultaneous Multi-Threading (SMT)
Extending Roofline: The ECM performance model
Optional: Pattern-based performance engineering
Lecturers:
Georg Hager and Gerhard Wellein (RRZE / HPC, Uni. Erlangen)
Language:
English
Date, Time, and Location:
December 5-7, 2018, 9am - 5pm,
FH Internet-Raum FH1 (TU Wien, Wiedner Hauptstraße 8-10, ground floor, red area)